1. Field of the Invention
This invention relates to variable delay lines, and more particularly relates to a circuit technique to avoid glitches from a variable delay line.
2. Description of Related Art
Digital delay lock loops (DLL's), such as the one shown in FIG. 7, typically employ a variable delay line 86 and phase detect mechanism 88. The variable delay line is generally constructed with delay units and multiplexers in order to provide a clock signal with varying amounts of delay. The amount of delay may be chosen by selectively tapping off the outputs of the delay units and feeding the signals into a multiplexer tree. For example, referring to FIG. 3, a variable delay line 60 is shown that includes a clock signal 62, delay units 64 comprised of inverter gates, a select mechanism 68, a multiplexer (i.e., MUX) 66, and an output 70. According to this example, if the desired output 70 is signal A, which in this case is a clock signal 62 with no delay, the select mechanism 68 outputs a select signal SEL of "0" to the multiplexer 66. This causes the multiplexer 66 to output clock signal 62. Alternatively, if signal B is desired at output 70, the select mechanism 68 sends a select signal SEL of value "1" to multiplexer 66 which will allow signal B to pass to output 70. Signal B comprises clock signal 62 with a predetermined amount of delay caused by the inverters 64. Unfortunately, under this known system, depending on the timing relationship between the delay line input clock signal 62 and the multiplexer select signals, a glitch can occur at the output 70 of the variable delay line 60.
For example, referring to FIG. 4, which depicts the timing diagram of variable delay line 60, it can be seen that in the case where the select mechanism 68 switches multiplexer 66 from signal A to signal B, it is possible that the select signal SEL may arrive at the multiplexer 66 after signal A but before signal B. The result in output signal 70 is a glitch 72 which can have a harmful effect on the system and operations being performed. Therefore, without some improved mechanism for eliminating glitches in variable delay lines, potential errors will be unavoidable.